Esercitazioni pratiche di elettronica/Logica Sequenziale/Macchine a Stati Finiti
Automi di Mealy e di Moore
modificaLa differenza fondamentale tra un ASF di Mealy e un ASF di Moore è la seguente:
* Nel modello di Mealy le uscite sono funzione sia degli stati che degli ingressi: W: QxI → U * Nel modello di Moore le uscite sono funzioni solo degli stati: W: Q → U
È stato dimostrato che i due modelli sono equivalenti e che è possibile trasformare un automa di Mealy in uno di Moore che esibisce lo stesso comportamento terminale.
Grapho della Macchina a Stati
modificaESEMPI:
modificaContatore Up & Down
modificaFile VHDL della Macchina a Stati
modificaLIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY SHELL_UPDWCOUN IS PORT (CLK,C,RESET: IN std_logic; Y0,Y1,Y2 : OUT std_logic); END;
ARCHITECTURE BEHAVIOR OF SHELL_UPDWCOUN IS
SIGNAL STATE0, next_STATE0, STATE1, next_STATE1, STATE2, next_STATE2, STATE3 , next_STATE3, STATE4, next_STATE4, STATE6, next_STATE6 : std_logic; SIGNAL next_Y0,next_Y1,next_Y2 : std_logic; SIGNAL Y : std_logic_vector (2 DOWNTO 0); BEGIN
PROCESS (CLK, RESET, next_STATE0, next_STATE1, next_STATE2, next_STATE3, next_STATE4, next_STATE6, next_Y2, next_Y1, next_Y0) BEGIN IF ( RESET='1' ) THEN STATE0 <= '1'; STATE1 <= '0'; STATE2 <= '0'; STATE3 <= '0'; STATE4 <= '0'; STATE6 <= '0'; Y2 <= '0'; Y1 <= '0'; Y0 <= '0'; ELSIF CLK='1' AND CLK'event THEN STATE0 <= next_STATE0; STATE1 <= next_STATE1; STATE2 <= next_STATE2; STATE3 <= next_STATE3; STATE4 <= next_STATE4; STATE6 <= next_STATE6; Y2 <= next_Y2; Y1 <= next_Y1; Y0 <= next_Y0; END IF; END PROCESS;
PROCESS (C,STATE0,STATE1,STATE2,STATE3,STATE4,STATE6,Y) BEGIN
IF (( C='1' AND (STATE1='1')) OR ( C='0' AND (STATE6='1'))) THEN next_STATE0<='1'; ELSE next_STATE0<='0'; END IF;
IF (( C='0' AND (STATE0='1')) OR ( C='1' AND (STATE2='1'))) THEN next_STATE1<='1'; ELSE next_STATE1<='0'; END IF;
IF (( C='0' AND (STATE1='1')) OR ( C='1' AND (STATE3='1'))) THEN next_STATE2<='1'; ELSE next_STATE2<='0'; END IF;
IF (( C='0' AND (STATE2='1')) OR ( C='1' AND (STATE4='1'))) THEN next_STATE3<='1'; ELSE next_STATE3<='0'; END IF;
IF (( C='0' AND (STATE3='1')) OR ( C='1' AND (STATE6='1'))) THEN next_STATE4<='1'; ELSE next_STATE4<='0'; END IF;
IF (( C='1' AND (STATE0='1')) OR ( C='0' AND (STATE4='1'))) THEN next_STATE6<='1'; ELSE next_STATE6<='0'; END IF;
Y<= (( std_logic_vector'( STATE1, STATE1, STATE1)) AND ((
std_logic_vector'( C, C, C)) ) AND (std_logic_vector'("000") ) ) OR ((
std_logic_vector'( STATE6, STATE6, STATE6)) AND (( std_logic_vector'( NOT C
, NOT C, NOT C)) ) AND (std_logic_vector'("000") ) ) OR ((
std_logic_vector'( STATE0, STATE0, STATE0)) AND (( std_logic_vector'( NOT C
, NOT C, NOT C)) ) AND (std_logic_vector'("001") ) ) OR ((
std_logic_vector'( STATE2, STATE2, STATE2)) AND (( std_logic_vector'( C, C,
C)) ) AND (std_logic_vector'("001") ) ) OR (( std_logic_vector'( STATE1,
STATE1, STATE1)) AND (( std_logic_vector'( NOT C, NOT C, NOT C)) ) AND (
std_logic_vector'("010") ) ) OR (( std_logic_vector'( STATE3, STATE3,
STATE3)) AND (( std_logic_vector'( C, C, C)) ) AND (std_logic_vector'(
"010") ) ) OR (( std_logic_vector'( STATE2, STATE2, STATE2)) AND ((
std_logic_vector'( NOT C, NOT C, NOT C)) ) AND (std_logic_vector'("011") ) )
OR (( std_logic_vector'( STATE4, STATE4, STATE4)) AND ((
std_logic_vector'( C, C, C)) ) AND (std_logic_vector'("011") ) ) OR ((
std_logic_vector'( STATE3, STATE3, STATE3)) AND (( std_logic_vector'( NOT C
, NOT C, NOT C)) ) AND (std_logic_vector'("100") ) ) OR ((
std_logic_vector'( STATE6, STATE6, STATE6)) AND (( std_logic_vector'( C, C,
C)) ) AND (std_logic_vector'("100") ) ) OR (( std_logic_vector'( STATE0,
STATE0, STATE0)) AND (( std_logic_vector'( C, C, C)) ) AND (
std_logic_vector'("110") ) ) OR (( std_logic_vector'( STATE4, STATE4,
STATE4)) AND (( std_logic_vector'( NOT C, NOT C, NOT C)) ) AND (
std_logic_vector'("110") ) );
next_Y2 <= Y(2); next_Y1 <= Y(1); next_Y0 <= Y(0); END PROCESS;
END BEHAVIOR;
LIBRARY ieee; USE ieee.std_logic_1164.all;
ENTITY UPDWCOUN IS PORT (Y : OUT std_logic_vector (2 DOWNTO 0); CLK,C,RESET: IN std_logic); END;
ARCHITECTURE BEHAVIOR OF UPDWCOUN IS COMPONENT SHELL_UPDWCOUN PORT (CLK,C,RESET: IN std_logic; Y0,Y1,Y2 : OUT std_logic); END COMPONENT; BEGIN SHELL1_UPDWCOUN : SHELL_UPDWCOUN PORT MAP (CLK=>CLK,C=>C,RESET=>RESET,Y0=>Y( 0),Y1=>Y(1),Y2=>Y(2)); END BEHAVIOR;