Elettronica pratica/Porte logiche fondamentali: differenze tra le versioni

Contenuto cancellato Contenuto aggiunto
cambio avanzamento a 50%
Riga 20:
::::::#NAND
::::::#NOR
 
===Spiegazione del funzionamento delle porte===
 
1. Porta AND
 
*L'uscita della porta AND è 1 se entrambi i suoi due ingressi sono 1; altrimenti, l'uscita sarà 0.
 
[[Image:And.svg|thumb|center|128px|AND gate]]
 
<table border=1 align=center cellpadding=5>
<caption>AND</caption>
<tr>
<td>A</td>
<td>B</td>
<td>X</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>0</td>
</tr><tr>
<td>1</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
</table>
 
2. Porta OR
 
*L'uscita della porta OR è 1 se uno o l'altro dei suoi due ingressi sono 0; altrimenti, l'uscita sarà 0.
 
[[Image:Or-gate-en.svg|thumb|center|128px|OR gate]]
 
<table border=1 align=center cellpadding=5>
<caption>OR</caption>
<tr>
<td>A</td>
<td>B</td>
<td>X</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
</tr><tr>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>1</td>
</tr>
</table>
 
3. Porta NOT
 
*L'uscita dalla porta NOT è sempre uguale all'oposto del suo ingresso.
 
[[Image:Not-gate-en.svg|thumb|center|128px|NOT gate]]
 
<table border=1 align=center cellpadding=5>
<caption>NOT</caption>
<tr>
<td>A</td>
<td>X</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>0</td>
</tr>
</table>
 
4. Porta NAND
 
*As if a NOT gate had been stuck on the end of an AND gate; i.e., if both inputs are 1, the output will be 0, else it will be 1
 
[[Image:Nand-gate-en.svg|thumb|center|128px|NAND gate]]
 
<table border=1 align=center cellpadding=5>
<caption>NAND</caption>
<tr>
<td>A</td>
<td>B</td>
<td>X</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
</tr><tr>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
</table>
 
5. NOR Gate
 
*As if a NOT gate had been stuck on the end of an OR gate; i.e., if either input is 1, the output will be 0, else it will be 1
 
[[Image:Nor-gate-en.svg|thumb|center|128px|NOR gate]]
 
<table border=1 align=center cellpadding=5>
<caption>NOR</caption>
<tr>
<td>A</td>
<td>B</td>
<td>X</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>0</td>
</tr><tr>
<td>1</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
</table>
 
6. XOR gate
 
*This gate is identical to the OR gate except for when the inputs are the same - in this case it is 0 as well
 
[[Image:Xor-gate-en.svg|thumb|center|128px|XOR gate]]
 
<table border=1 align=center cellpadding=5>
<caption>XOR</caption>
<tr>
<td>A</td>
<td>B</td>
<td>X</td>
</tr>
<tr>
<td>0</td>
<td>0</td>
<td>0</td>
</tr>
<tr>
<td>0</td>
<td>1</td>
<td>1</td>
</tr><tr>
<td>1</td>
<td>0</td>
<td>1</td>
</tr>
<tr>
<td>1</td>
<td>1</td>
<td>0</td>
</tr>
</table>
 
[[Categoria:Elettronica pratica]]
{{Avanzamento|50%|3 aprile 2008}}